/* ------------------------------------------------------------------------- */
/*  @file:    startup_MM32F5277e.s                                           */
/*  @purpose: CMSIS Cortex-M33 Core Device Startup File                      */
/*                                                                           */
/*  @version: 1.0                                                            */
/*  @date:    2022-03-03                                                     */
/*  @build:   b220303                                                        */
/* ------------------------------------------------------------------------- */
/*                                                                           */
/* Copyright 2022 MindMotion                                                 */
/* All rights reserved.                                                      */
/*                                                                           */
/* SPDX-License-Identifier: BSD-3-Clause                                     */
/*****************************************************************************/
/* Version: GCC for ARM Embedded Processors                                  */
/*****************************************************************************/
    .syntax unified
    .arch armv8-m.main

    .section .isr_vector, "a"
    .align 2
    .globl __isr_vector
__isr_vector:
    .long   __StackTop                                      /* Top of Stack */
    .long   Reset_Handler                                   /* Reset Handler */
    .long   NMI_Handler                                     /* NMI Handler*/
    .long   HardFault_Handler                               /* Hard Fault Handler*/
    .long   MemManage_Handler                               /* MPU Fault Handler*/
    .long   BusFault_Handler                                /* Bus Fault Handler*/
    .long   UsageFault_Handler                              /* Usage Fault Handler*/
    .long   0                                               /* Reserved*/
    .long   0                                               /* Reserved*/
    .long   0                                               /* Reserved*/
    .long   0                                               /* Reserved*/
    .long   SVC_Handler                                     /* SVCall Handler*/
    .long   DebugMon_Handler                                /* Debug Monitor Handler*/
    .long   0                                               /* Reserved*/
    .long   PendSV_Handler                                  /* PendSV Handler*/
    .long   SysTick_Handler                                 /* SysTick Handler*/

    .long   WWDG_IWDG_IRQHandler                            /* 0  Watchdog interrupt (IWDG is EXTI21) */
    .long   PVD_IRQHandler                                  /* 1  Supply Voltage Detect (PVD) Interrupt (EXTI16) */
    .long   BKP_TAMPER_IRQHandler                           /* 2  BKP intrusion detection interrupted */
    .long   RTC_IRQHandler                                  /* 3  RTC global interrupt */
    .long   FLASH_IRQHandler                                /* 4  Flash Global Interrupt */
    .long   RCC_CRS_IRQHandler                              /* 5  RCC and CRS global interrupt */
    .long   EXTI0_IRQHandler                                /* 6  EXTI line 0 interrupt */
    .long   EXTI1_IRQHandler                                /* 7  EXTI line 1 interrupt */
    .long   EXTI2_IRQHandler                                /* 8  EXTI line 2 interrupt */
    .long   EXTI3_IRQHandler                                /* 9  EXTI line 3 interrupt */
    .long   EXTI4_IRQHandler                                /* 10  EXTI line 4 interrupt */
    .long   DMA1_CH1_IRQHandler                             /* 11  DMA1 channel 1 global interrupt */
    .long   DMA1_CH2_IRQHandler                             /* 12  DMA1 channel 2 global interrupt */
    .long   DMA1_CH3_IRQHandler                             /* 13  DMA1 channel 3 global interrupt */
    .long   DMA1_CH4_IRQHandler                             /* 14  DMA1 channel 4 global interrupt */
    .long   DMA1_CH5_IRQHandler                             /* 15  DMA1 channel 5 global interrupt */
    .long   DMA1_CH6_IRQHandler                             /* 16  DMA1 channel 6 global interrupt */
    .long   DMA1_CH7_IRQHandler                             /* 17  DMA1 channel 7 global interrupt */
    .long   ADC1_2_IRQHandler                               /* 18  ADC1/2 global interrupt */
    .long   0                                               /* 19  Reserved */
    .long   DMA1_CH8_IRQHandler                             /* 20  DMA1 channel 8 global interrupt */
    .long   FlexCAN1_IRQHandler                             /* 21  FlexCAN1 global interrupt */
    .long   0                                               /* 22  Reserved */
    .long   EXTI9_5_IRQHandler                              /* 23  EXTI line[9:5] interrupt */
    .long   TIM1_BRK_IRQHandler                             /* 24  TIM1 brake interrupt */
    .long   TIM1_UP_IRQHandler                              /* 25  TIM1 update interrupted */
    .long   TIM1_TRG_COM_IRQHandler                         /* 26  TIM1 trigger/COM interrupt */
    .long   TIM1_CC_IRQHandler                              /* 27  TIM1 capture compare interrupt */
    .long   TIM2_IRQHandler                                 /* 28  TIM2 global interrupt */
    .long   TIM3_IRQHandler                                 /* 29  TIM3 global interrupt */
    .long   TIM4_IRQHandler                                 /* 30  TIM4 global interrupt */
    .long   I2C1_IRQHandler                                 /* 31  I2C1 global interrupt */
    .long   0                                               /* 32  Reserved */
    .long   I2C2_IRQHandler                                 /* 33  I2C2 global interrupt */
    .long   0                                               /* 34  Reserved */
    .long   SPI1_IRQHandler                                 /* 35  SPI1 global interrupt */
    .long   SPI2_IRQHandler                                 /* 36  SPI2 global interrupt */
    .long   UART1_IRQHandler                                /* 37  UART1 global interrupt */
    .long   UART2_IRQHandler                                /* 38  UART2 global interrupt */
    .long   UART3_IRQHandler                                /* 39  UART3 global interrupt */
    .long   EXTI15_10_IRQHandler                            /* 40  Interrupt on EXTI line[15:10] */
    .long   RTC_ALR_IRQHandler                              /* 41  RTC Alarm Interrupt (EXTI17) */
    .long   USB_WKUP_IRQHandler                             /* 42  USB Wakeup Interrupt (EXTI18) */
    .long   TIM8_BRK_IRQHandler                             /* 43  TIM8 brake interrupt */
    .long   TIM8_UP_IRQHandler                              /* 44  TIM8 update interrupted */
    .long   TIM8_TRG_COM_IRQHandler                         /* 45  TIM8 trigger/COM interrupt */
    .long   TIM8_CC_IRQHandler                              /* 46  TIM8 capture compare interrupt */
    .long   0                                               /* 47  Reserved */
    .long   0                                               /* 48  Reserved */
    .long   0                                               /* 49  Reserved */
    .long   TIM5_IRQHandler                                 /* 50  TIM5 global interrupt */
    .long   SPI3_IRQHandler                                 /* 51  SPI3 global interrupt */
    .long   UART4_IRQHandler                                /* 52  UART4 global interrupt */
    .long   UART5_IRQHandler                                /* 53  UART5 global interrupt */
    .long   TIM6_IRQHandler                                 /* 54  TIM6 global interrupt */
    .long   TIM7_IRQHandler                                 /* 55  TIM7 global interrupt */
    .long   DMA2_CH1_IRQHandler                             /* 56  DMA2 channel 1 global interrupt */
    .long   DMA2_CH2_IRQHandler                             /* 57  DMA2 channel 2 global interrupt */
    .long   DMA2_CH3_IRQHandler                             /* 58  DMA2 channel 3 global interrupt */
    .long   DMA2_CH4_IRQHandler                             /* 59  DMA2 channel 4 global interrupt */
    .long   DMA2_CH5_IRQHandler                             /* 60  DMA2 channel 5 global interrupt */
    .long   ENET_IRQHandler                                 /* 61  ENET global interrupt */
    .long   ENET_WKUP_IRQHandler                            /* 62  ENET wake-up interrupt (EXTI25) */
    .long   0                                               /* 63  Reserved */
    .long   COMP_IRQHandler                                 /* 64  Comparator 1/2/3 Global Interrupts (EXTI19/20/24) */
    .long   FlexCAN2_IRQHandler                             /* 65  FLexCAN2 global interrupt */
    .long   0                                               /* 66  Reserved */
    .long   USB_FS_IRQHandler                               /* 67  USB OTG global interrupt */
    .long   DMA2_CH6_IRQHandler                             /* 68  DMA2 channel 6 global interrupt */
    .long   DMA2_CH7_IRQHandler                             /* 69  DMA2 channel 7 global interrupt */
    .long   DMA2_CH8_IRQHandler                             /* 70  DMA2 channel 8 global interrupt */
    .long   UART6_IRQHandler                                /* 71  UART6 global interrupt */
    .long   0                                               /* 72  Reserved */
    .long   0                                               /* 73  Reserved */
    .long   0                                               /* 74  Reserved */
    .long   0                                               /* 75  Reserved */
    .long   0                                               /* 76  Reserved */
    .long   0                                               /* 77  Reserved */
    .long   0                                               /* 78  Reserved */
    .long   0                                               /* 79  Reserved */
    .long   0                                               /* 80  Reserved */
    .long   0                                               /* 81  Reserved */
    .long   UART7_IRQHandler                                /* 82  UART7 global interrupt */
    .long   0                                               /* 83  Reserved */
    .long   0                                               /* 84  Reserved */
    .long   0                                               /* 85  Reserved */
    .long   0                                               /* 86  Reserved */
    .long   0                                               /* 87  Reserved */
    .long   0                                               /* 88  Reserved */
    .long   0                                               /* 89  Reserved */
    .long   0                                               /* 90  Reserved */
    .long   0                                               /* 91  Reserved */
    .long   0                                               /* 92  Reserved */
    .long   0                                               /* 93  Reserved */
    .long   0                                               /* 94  Reserved */
    .long   QSPI_IRQHandler                                 /* 95  QSPI global interrupt */
    .long   0                                               /* 96  Reserved */
    .long   0                                               /* 97  Reserved */
    .long   0                                               /* 98  Reserved */
    .long   0                                               /* 99  Reserved */
    .long   0                                               /* 100  Reserved */
    .long   0                                               /* 101  Reserved */
    .long   LPTIM_IRQHandler                                /* 102  LPTIM global interrupt (EXTI22) */
    .long   0                                               /* 103  Reserved */
    .long   LPUART_IRQHandler                               /* 104  LPUART global interrupt (EXTI23) */

    .long   DefaultISR                                                /* 254*/

    .size    __isr_vector, . - __isr_vector



    .text
    .thumb

/* Reset Handler */

    .thumb_func
    .align 2
    .globl   Reset_Handler
    .weak    Reset_Handler
    .type    Reset_Handler, %function
Reset_Handler:
    cpsid   i               /* Mask interrupts */
    .equ    VTOR, 0xE000ED08
    ldr     r0, =VTOR
    ldr     r1, =__isr_vector
    str     r1, [r0]
    ldr     r2, [r1]
    msr     msp, r2
#ifndef __NO_SYSTEM_INIT
    ldr   r0,=SystemInit
    blx   r0
#endif
/*     Loop to copy data from read only memory to RAM. The ranges
 *      of copy from/to are specified by following symbols evaluated in
 *      linker script.
 *      __etext: End of code section, i.e., begin of data sections to copy from.
 *      __data_start__/__data_end__: RAM address range that data should be
 *      __noncachedata_start__/__noncachedata_end__ : none cachable region
 *      copied to. Both must be aligned to 4 bytes boundary.  */

    ldr    r1, =__etext
    ldr    r2, =__data_start__
    ldr    r3, =__data_end__

#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
 * and the second one favors code size. Default uses the second one.
 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
    subs    r3, r2
    ble    .LC1
.LC0:
    subs    r3, #4
    ldr    r0, [r1, r3]
    str    r0, [r2, r3]
    bgt    .LC0
.LC1:
#else  /* code size implemenation */
.LC0:
    cmp     r2, r3
    ittt    lt
    ldrlt   r0, [r1], #4
    strlt   r0, [r2], #4
    blt    .LC0
#endif
#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
    ldr    r2, =__noncachedata_start__
    ldr    r3, =__noncachedata_init_end__
#ifdef __PERFORMANCE_IMPLEMENTATION
/* Here are two copies of loop implementations. First one favors performance
 * and the second one favors code size. Default uses the second one.
 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
    subs    r3, r2
    ble    .LC3
.LC2:
    subs    r3, #4
    ldr    r0, [r1, r3]
    str    r0, [r2, r3]
    bgt    .LC2
.LC3:
#else  /* code size implemenation */
.LC2:
    cmp     r2, r3
    ittt    lt
    ldrlt   r0, [r1], #4
    strlt   r0, [r2], #4
    blt    .LC2
#endif
/* zero inited ncache section initialization */
    ldr r3, =__noncachedata_end__
    movs    r0,0
.LC4:
    cmp    r2,r3
    itt    lt
    strlt   r0,[r2],#4
    blt    .LC4
#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */

#ifdef __STARTUP_CLEAR_BSS
/*     This part of work usually is done in C library startup code. Otherwise,
 *     define this macro to enable it in this startup.
 *
 *     Loop to zero out BSS section, which uses following symbols
 *     in linker script:
 *      __bss_start__: start of BSS section. Must align to 4
 *      __bss_end__: end of BSS section. Must align to 4
 */
    ldr r1, =__bss_start__
    ldr r2, =__bss_end__

    movs    r0, 0
.LC5:
    cmp     r1, r2
    itt    lt
    strlt   r0, [r1], #4
    blt    .LC5
#endif /* __STARTUP_CLEAR_BSS */

    cpsie   i               /* Unmask interrupts */
#ifndef __START
#define __START _start
#endif
#ifndef __ATOLLIC__
    ldr   r0,=__START
    blx   r0
#else
    ldr   r0,=__libc_init_array
    blx   r0
    ldr   r0,=main
    bx    r0
#endif
    .pool
    .size Reset_Handler, . - Reset_Handler

# DefaultISR
    .align  1
    .thumb_func
    .weak DefaultISR
    .type DefaultISR, %function
DefaultISR:
    b DefaultISR
    .size DefaultISR, . - DefaultISR

# NMI_Handler
    .align 1
    .thumb_func
    .weak NMI_Handler
    .type NMI_Handler, %function
NMI_Handler:
    ldr   r0,=NMI_Handler
    bx    r0
    .size NMI_Handler, . - NMI_Handler

# HardFault_Handler
    .align 1
    .thumb_func
    .weak HardFault_Handler
    .type HardFault_Handler, %function
HardFault_Handler:
    ldr   r0,=HardFault_Handler
    bx    r0
    .size HardFault_Handler, . - HardFault_Handler

# MemManage_Handler
# BusFault_Handler
# UsageFault_Handler
# DebugMon_Handler

# SVC_Handler
    .align 1
    .thumb_func
    .weak SVC_Handler
    .type SVC_Handler, %function
SVC_Handler:
    ldr   r0,=SVC_Handler
    bx    r0
    .size SVC_Handler, . - SVC_Handler

# PendSV_Handler
    .align 1
    .thumb_func
    .weak PendSV_Handler
    .type PendSV_Handler, %function
PendSV_Handler:
    ldr   r0,=PendSV_Handler
    bx    r0
    .size PendSV_Handler, . - PendSV_Handler

# SysTick_Handler
    .align 1
    .thumb_func
    .weak SysTick_Handler
    .type SysTick_Handler, %function
SysTick_Handler:
    ldr   r0,=SysTick_Handler
    bx    r0
    .size SysTick_Handler, . - SysTick_Handler


/*    Macro to define default handlers. Default handler
 *    will be weak symbol and just dead loops. They can be
 *    overwritten by other handlers */
    .macro def_irq_handler  handler_name
    .weak \handler_name
    .set  \handler_name, DefaultISR
    .endm

/* Exception Handlers */
    def_irq_handler    MemManage_Handler
    def_irq_handler    BusFault_Handler
    def_irq_handler    UsageFault_Handler
    def_irq_handler    DebugMon_Handler


    def_irq_handler    WWDG_IWDG_IRQHandler
    def_irq_handler    PVD_IRQHandler
    def_irq_handler    BKP_TAMPER_IRQHandler
    def_irq_handler    RTC_IRQHandler
    def_irq_handler    FLASH_IRQHandler
    def_irq_handler    RCC_CRS_IRQHandler
    def_irq_handler    EXTI0_IRQHandler
    def_irq_handler    EXTI1_IRQHandler
    def_irq_handler    EXTI2_IRQHandler
    def_irq_handler    EXTI3_IRQHandler
    def_irq_handler    EXTI4_IRQHandler
    def_irq_handler    DMA1_CH1_IRQHandler
    def_irq_handler    DMA1_CH2_IRQHandler
    def_irq_handler    DMA1_CH3_IRQHandler
    def_irq_handler    DMA1_CH4_IRQHandler
    def_irq_handler    DMA1_CH5_IRQHandler
    def_irq_handler    DMA1_CH6_IRQHandler
    def_irq_handler    DMA1_CH7_IRQHandler
    def_irq_handler    ADC1_2_IRQHandler
    def_irq_handler    DMA1_CH8_IRQHandler
    def_irq_handler    FlexCAN1_IRQHandler
    def_irq_handler    EXTI9_5_IRQHandler
    def_irq_handler    TIM1_BRK_IRQHandler
    def_irq_handler    TIM1_UP_IRQHandler
    def_irq_handler    TIM1_TRG_COM_IRQHandler
    def_irq_handler    TIM1_CC_IRQHandler
    def_irq_handler    TIM2_IRQHandler
    def_irq_handler    TIM3_IRQHandler
    def_irq_handler    TIM4_IRQHandler
    def_irq_handler    I2C1_IRQHandler
    def_irq_handler    I2C2_IRQHandler
    def_irq_handler    SPI1_IRQHandler
    def_irq_handler    SPI2_IRQHandler
    def_irq_handler    UART1_IRQHandler
    def_irq_handler    UART2_IRQHandler
    def_irq_handler    UART3_IRQHandler
    def_irq_handler    EXTI15_10_IRQHandler
    def_irq_handler    RTC_ALR_IRQHandler
    def_irq_handler    USB_WKUP_IRQHandler
    def_irq_handler    TIM8_BRK_IRQHandler
    def_irq_handler    TIM8_UP_IRQHandler
    def_irq_handler    TIM8_TRG_COM_IRQHandler
    def_irq_handler    TIM8_CC_IRQHandler
    def_irq_handler    TIM5_IRQHandler
    def_irq_handler    SPI3_IRQHandler
    def_irq_handler    UART4_IRQHandler
    def_irq_handler    UART5_IRQHandler
    def_irq_handler    TIM6_IRQHandler
    def_irq_handler    TIM7_IRQHandler
    def_irq_handler    DMA2_CH1_IRQHandler
    def_irq_handler    DMA2_CH2_IRQHandler
    def_irq_handler    DMA2_CH3_IRQHandler
    def_irq_handler    DMA2_CH4_IRQHandler
    def_irq_handler    DMA2_CH5_IRQHandler
    def_irq_handler    ENET_IRQHandler
    def_irq_handler    ENET_WKUP_IRQHandler
    def_irq_handler    COMP_IRQHandler
    def_irq_handler    FlexCAN2_IRQHandler
    def_irq_handler    USB_FS_IRQHandler
    def_irq_handler    DMA2_CH6_IRQHandler
    def_irq_handler    DMA2_CH7_IRQHandler
    def_irq_handler    DMA2_CH8_IRQHandler
    def_irq_handler    UART6_IRQHandler
    def_irq_handler    UART7_IRQHandler
    def_irq_handler    QSPI_IRQHandler
    def_irq_handler    LPTIM_IRQHandler
    def_irq_handler    LPUART_IRQHandler

    .end
